ACC example has data state variables assigned from output ports.
In ACC example (and likewise in ACC Refinement example) in component
SpeedPlausibilization transition Reset a DSV is assigned the value of an
output port.
There is currently no constraint checker to cover this case.
Since Bernhard build this example, I guess that he assumed output ports
to be readable (w.r.t his Habil).
So the question is whether we want have output ports to be readable.
I vote for extending the constraint checker to restrict:
(a) input ports to be READ-ONLY (expressions and right-hand side of
assignments) [we already have that!]
(b) output ports to be WRITE-ONLY (left-hand side of assignments only)
(from redmine: issue id 831, created on 2012-05-29, closed on 2012-06-11)
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