Allocation Editor: Feasiblity of port allocation should consider sub-types
Steps to reproduce
- Import the attached model
- Open the Components ->Hardware allocation
- Switch to the Ports ->Transceiver tab to see that
Component.Output
is allocated toGeneric_ECU.Generic_Bus_Controller
. - Switch to the OutputPorts ->Transmitter tab
- The allocation of
Component.Output
toGeneric_ECU.Generic_Actuator
is shown as feasible (i.e., not grayed out as it would be expected) - However, it is not possible to actually create such an allocation.
- The allocation of
Analysis:
- The same can also be observed for allocations from the Task or Partition Architecture to the Platform Architecture
- The reason for this is that different allocation entry types are used to map Ports to Transceivers, OutputPorts to Transmitters, and InputPorts to Receivers.
- Proposed solution: the editors for the derived types (i.e., InputPorts and OutputPorts) must be made aware of the potential allocation of the super type (Port)
(from redmine: issue id 3561, created on 2018-10-24, closed on 2018-11-13)
- Uploads:
- PortAllocationTest.af3_23 Test case for {CA, TA, PA}->HW allocations