Simulation of strongly causal components with internal variables is not correct
Simulating a strongly causal component with internal variables has strange behaviour. Output ports need two time steps instead of one time step, if the internal variable is involved.
Example:
see attached schreenshots
(from redmine: issue id 1414, created on 2013-06-12, closed on 2013-09-04)
- Relations:
- relates #1657 (closed)
- relates #595 (closed)
- Uploads: